page 1 qw -jp002 rev :b comchip t echnology co., l td. CSRS045V0P-HF rohs device features esd protected for 2 high speed i/o ports iec61000-4-2 (esd) 8kv (contact) ,15kv(air). iec61000-4-4 (fet)(5/50ns) level-3, 20a for i/o 40a for power . iec61000-4-5 (lightning) 6a(8/20us) w orking voltage: 5v low capacitance:1.2pf(t yp.). fast turn-on and low clamping voltage. mechanical data case: sot -143 standard package, molded plastic. t erminals: solder plated, solderable per mil-std-750,method 2026. dimensions in inches and (millimeters) sot -143 pin configuration circuit diagram 0.043(1.10) 0.035(0.89) 0.030(0.76) 0.004(0.10) 0.035(0.90) vdd gnd 4 3 2 1 i/o 2 4 3 2 1 i/o 1 0.120(3.04) 0.055(1.40) 0.1 10(2.80) 0.047(1.20) 0.024(0.60) 0.100(2.55) 0.007(0.18) 0.004(0.09) 0.089(2.25) low capacitance esd protection array w eight: 0.0108 gram(approx.). 0.002(0.05) 0.080(2.02) 0.071(1.80) 0.038(0.96)bsc 0.0078(0.20)bsc 0.012(0.30) 0.020(0.50) 0.014(0.35) halogen free c o m c h i p s m d d i o d e s p e c i a l i s t
kv v a 17 6 6 v esd v dc i pp c c 260 ( 10 sec) -55 to +150 -55 to +85 t sol t j lead soldering temperature operating temperature esd per iec 61000-4-2(air) operating supply voltage peak pulse current ( tp = 8/20 us) parameter symbol v alue unit maximum rating (at t a =25c unless otherwise noted) esd per iec 61000-4-2(contact) storage temperature dc voltage at any i/o pin t stg v io (gnd -0.5) to (vdd +0.5) 12 c v ua v 5 i leak v r wm reverse leakage current reverse stand-off voltage parameter conditions symbol min t yp max unit v r wm = 5 v , t=25c, pin 4 to pin 1 pin 4 to pin 1 electrical characteristics (at t a =25c unless otherwise noted) v pin 4 v pin 1 = = 5 v , 0v , t=25c diode breakdown voltage i r = 1 ma, pin 4 to pin 1 , t=25c, v bv forward voltage i f = 15 ma, pin 1 to pin 4 , t=25c, v f v 1 esd holding v oltage any channel pin to ground = 5 a, tp=8/20us , t=25c, i pp v cl v 13 8.1 0.8 6.2 1.2 channel to channel input capacitance v pin4 = 5v ,v pin1 = 0v , v in =2.5v , f = 1mhz,any channel pin to ground 1.4 v pin4 = 5v ,v pin1 = 0v , v in =2.5v f = 1mhz,between channel pin 0.1 pf 0.12 v pin4 = 5v ,v pin1 = 0v , v in =2.5v f = 1mhz,channel_x pin to ground - channel_y pin to ground 0.04 0.06 2 9 1 v page 2 qw -jp002 rev :b comchip t echnology co., l td. low capacitance esd protection array iec 61000-4-2 +6kv , t=25c, pin to ground contact mode any channel clamping voltage channel input capacitance v oltage of channel input capacitance c in c cross ?c in v hold v pf pf i ch-leak ua channel leakage current c o m c h i p s m d d i o d e s p e c i a l i s t
t emperature, c ) ( i n p u t c a p a c i t a n c e , ( p f ) t ransmission line pulsing tlp v oltage, ( ) ( v ) page 3 qw -jp002 rev :b comchip t echnology co., l td. ra ting and characteristic cur ves (CSRS045V0P-HF) fig. 1 - power derating curve fig. 2 - clamping voltage vs. peak pulse current fig.3 - forward voltage v .s. forward current fig.4 - t ypical variation of c in v .s. v in ambient t emperature , t a ( c ) peak pulse current, a ( ) c l a m p i n g v o l t a g e , ( v ) w aveform parameters : s s i / o pin to gnd pin peak pulse current, ( a ) f o r w a r d v o l t a g e , v ( ) w aveform parameters : s s i / o pin to gnd pin input v oltage, ( v ) i n p u t c a p a c i t a n c e , p f ( ) fig. 5 - t ypical variation of c in v .s. temperature fig. 6 - t ransmission line pulsing (tlp) measurement 0 2 4 6 8 1 0 1 2 1 4 v _ pulse pulse from a transmission line dut tlp _ i + - tlp _ v i / o to gnd 100ns 18 16 14 12 10 8 6 4 2 0 vdd=5v , gnd=0v , v =2.5v , f=1mhz in 1 10 100 90 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 tr=8 td=20 0 1 2 3 4 5 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 5.0 5.5 6.0 6.5 7.0 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 20 40 60 80 100 120 o vdd=5v , gnd=0v , f=1mhz, t=25 c tr =8 td =20 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 5.0 5.5 6.0 6.5 7.0 % o f r a t e d p o w e r o r i p p low capacitance esd protection array t r a n s m i s s i o n l i n e p u l s i n g t l p ( ) c u r r e n t , ( a ) c o m c h i p s m d d i o d e s p e c i a l i s t
page 4 qw -jp002 rev :b comchip t echnology co., l td. o 1 2 0 t railer device leader 10 pitches (min) 10 pitches (min) ....... ....... ....... ....... ....... ....... ....... ....... end start d 1 d 2 d w 1 t c direction of feed b c d d d 2 d 1 s o t - 1 4 3 s y m b o l a reel t aping specification ( m m ) ( i n c h ) 1 . 9 6 9 m i n . 3 . 1 9 0 . 1 0 2 . 8 0 0 . 1 0 4 . 0 0 0 . 1 0 1 . 5 5 0 . 1 0 3 . 5 0 0 . 0 5 1 . 7 5 0 . 1 0 5 0 . 0 m i n . 1 3 . 0 0 . 2 0 1 . 3 1 0 . 1 0 4 . 0 0 0 . 1 0 2 . 0 0 0 . 0 5 8 . 0 0 0 . 3 0 1 4 . 4 m a x . 1 7 8 1 0 . 1 1 0 0 . 0 0 4 0 . 1 2 6 0 . 0 0 4 0 . 0 5 2 0 . 0 0 4 0 . 0 6 1 0 . 0 0 4 7 . 0 0 8 0 . 0 4 0 0 . 5 1 2 0 . 0 0 8 s y m b o l ( m m ) ( i n c h ) 0 . 1 3 8 0 . 0 0 2 0 . 0 6 9 0 . 0 0 4 0 . 1 5 7 0 . 0 0 4 0 . 1 5 7 0 . 0 0 4 0 . 0 7 9 0 . 0 0 2 0 . 5 6 7 m a x e f p p 0 p 1 w w 1 s o t - 1 4 3 low capacitance esd protection array i n d e x h o l e d e f b w a p p 0 p 1 0 . 3 1 5 0 . 0 1 2 c o m c h i p s m d d i o d e s p e c i a l i s t
page 5 qw -jp002 rev :b comchip t echnology co., l td. b d f a low capacitance esd protection array marking code suggested p ad layout size (inch) 0.039 (mm) 1.00 1.40 1.40 0.055 0.055 sot -143 1.92 0.076 c1 1.72 0.068 a1 b c a standard packaging case t ype qty per reel (pcs) 3,000 sot -143 reel size (inch) 7 a a 1 a e c c 1 2.20 0.087 0.80 0.031 f 3.60 0.142 d e 2 1 4 3 part number CSRS045V0P-HF marking code c06xy c06 = device code x = date code y = control code c06xy c o m c h i p s m d d i o d e s p e c i a l i s t
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